? semiconductor components industries, llc, 2000 december, 2000 rev. 2 1 publication order number: mc74lcx125/d mc74lcx125 low-voltage cmos quad buffer with 5 vtolerant inputs and outputs (3state, noninverting) the mc74lcx125 is a high performance, noninverting quad buffer operating from a 2.3 to 3.6 v supply. high impedance ttl compatible inputs significantly reduce current loading to input drivers while ttl compatible outputs offer improved switching noise performance. a v i specification of 5.5 v allows mc74lcx125 inputs to be safely driven from 5 v devices. the mc74lcx125 is suitable for memory address driving and all ttl level bus oriented transceiver applications. current drive capability is 24 ma at the outputs. the output enable (oe n) inputs, when high, disable the outputs by placing them in a high z condition. ? designed for 2.3 to 3.6 v v cc operation ? 5 v tolerant interface capability with 5 v ttl logic ? supports live insertion and withdrawal ? i off specification guarantees high impedance when v cc = 0 v ? lvttl compatible ? lvcmos compatible ? 24 ma balanced output sink and source capability ? near zero static supply current in all three logic states (10 m a) substantially reduces system power requirements ? latchup performance exceeds 500 ma ? esd performance: human body model >2000 v; machine model >200 v http://onsemi.com device package shipping ordering information mc74lcx125d so14 55 units/rail mc74lcx125dr2 so14 mc74lcx125dt tssop14 2500 units/reel 96 untis/rail tssop14 dt suffix case 948g 14 1 soic eiaj14 m suffix case 965 so14 d suffix case 751a 14 1 marking diagrams 1 7 8 14 1 14 8 7 8 14 7 1 lcx 125 awlyww lcx125 alyw lcx125 awlyww a =assembly location wl or l = wafer lot y = year ww or w = work week mc74lcx125dtr2 tssop14 2500 units/reel mc74lcx125m soic eiaj14 50 units/rail mc74lcx125mel soic eiaj14 2000 units/reel 14 1
mc74lcx125 http://onsemi.com 2 figure 1. pinout: 14lead (top view) 13 14 12 11 10 9 8 2 1 34567 v cc oe 3d3 o3oe 2d2 o2 oe 0d0 o0oe 1 d1 o1 gnd pin names function output enable inputs data inputs 3state outputs pins oe n dn on h = high voltage level; l = low voltage level; z = high imped- ance state; x = high or low voltage level and transitions are acceptable, for i cc reasons, do not float inputs oe n dn on l l h l h x l h z inputs outputs function table d0 2 o0 3 oe 0 1 d1 5 o1 6 oe 1 4 d2 9 o2 8 oe 2 10 d3 12 o3 11 oe 3 13 figure 2. logic diagram absolute maximum ratings* symbol parameter value condition unit v cc dc supply voltage 0.5 to +7.0 v v i dc input voltage 0.5 v i +7.0 v v o dc output voltage 0.5 v o +7.0 output in 3state v 0.5 v o v cc + 0.5 output in high or low state. (note 1.) v i ik dc input diode current 50 v i < gnd ma i ok dc output diode current 50 v o < gnd ma +50 v o > v cc ma i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature range 65 to +150 c * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated co nditions is not implied. 1. i o absolute maximum rating must be observed.
mc74lcx125 http://onsemi.com 3 recommended operating conditions symbol parameter min typ max unit v cc supply voltage operating data retention only 2.0 1.5 2.5, 3.3 2.5, 3.3 3.6 3.6 v v i input voltage 0 5.5 v v o output voltage (high or low state) (3state) 0 0 v cc 5.5 v i oh high level output current v cc = 3.0 v 3.6 v v cc = 2.7 v 3.0 v v cc = 2.3 v 2.7 v 24 12 8 ma i ol low level output current v cc = 3.0 v 3.6 v v cc = 2.7 v 3.0 v v cc = 2.3 v 2.7 v + 24 + 12 + 8 ma t a operating freeair temperature 40 +85 c d t/ d v input transition rise or fall rate, v in from 0.8 v to 2.0 v, v cc = 3.0 v 0 10 ns/v dc electrical characteristics t a = 40 c to +85 c symbol characteristic condition min max unit v ih high level input voltage (note 2.) 2.3 v v cc 2.7 v 1.7 v ih g( ) 2.7 v v cc 3.6 v 2.0 v il low level input voltage (note 2.) 2.3 v v cc 2.7 v 0.7 v il g( ) 2.7 v v cc 3.6 v 0.8 v oh high level output voltage 2.3 v v cc 3.6 v; i ol = 100 m a v cc 0.2 v oh g v cc = 2.3 v; i oh = 8 ma 1.8 v cc = 2.7 v; i oh = 12 ma 2.2 v cc = 3.0 v; i oh = 18 ma 2.4 v cc = 3.0 v; i oh = 24 ma 2.2 v ol low level output voltage 2.3 v v cc 3.6 v; i ol = 100 m a 0.2 v ol g v cc = 2.3 v; i ol = 8 ma 0.6 v cc = 2.7 v; i ol = 12 ma 0.4 v cc = 3.0 v; i ol = 16 ma 0.4 v cc = 3.0 v; i ol = 24 ma 0.55 i i input leakage current 2.3 v v cc 3.6 v; 0 v v i 5.5 v 5 m a i cc quiescent supply current 2.3 v cc 3.6 v; v i = gnd or v cc 10 m a cc y 2.3 v cc 3.6 v; 3.6 v i or v o 5.5 v 10 m d i cc increase in i cc per input 2.3 v cc 3.6 v; v ih = v cc 0.6 v 500 m a 2. these values of v i are used to test dc electrical characteristics only.
mc74lcx125 http://onsemi.com 4 ac characteristics t r = t f = 2.5 ns; r l = 500 w limits unit t a = 40 c to +85 c v cc = 3.3 v 0.3 v v cc = 2.7 v v cc = 2.5 v 0.2 v c l = 50 pf c l = 50 pf c l = 30 pf symbol parameter waveform min max min max min max t plh t phl propagation delay time input to output 1 1.5 1.5 6.0 6.0 1.5 1.5 6.5 6.5 1.5 1.5 7.2 7.2 ns t pzh t pzl output enable time to high and low level 2 1.5 1.5 7.0 7.0 1.5 1.5 8.0 8.0 1.5 1.5 9.1 9.1 ns t phz t plz output disable time from high and low level 2 1.5 1.5 6.0 6.0 1.5 1.5 7.0 7.0 1.5 1.5 7.2 7.2 ns t oshl t oslh outputtooutput skew (note 3.) 1.0 1.0 ns 3. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same d evice. the specification applies to any outputs switching in the same direction, either hightolow (t oshl ) or lowtohigh (t oslh ); parameter guaranteed by design. dynamic switching characteristics t a = +25 c symbol characteristic condition min typ max unit v olp dynamic low peak voltage (note 4.) v cc = 3.3 v, c l = 50 pf, v ih = 3.3 v, v il = 0 v v cc =2.5 v, c l = 30 pf, v ih = 2.5 v, v il = 0 v 0.8 0.6 v v v olv dynamic low valley voltage (note 4.) v cc = 3.3 v, c l = 50 pf, v ih = 3.3 v, v il = 0 v v cc =2.5 v, c l = 30 pf, v ih = 2.5 v, v il = 0 v 0.8 0.6 v v 4. number of outputs defined as ano. measured with an1o outputs switching from hightolow or lowtohigh. the remaining output is measured in the low state. capacitive characteristics symbol parameter condition typical unit c in input capacitance v cc = 3.3 v, v i = 0 v or v cc 7 pf c out output capacitance v cc = 3.3 v, v i = 0 v or v cc 8 pf c pd power dissipation capacitance 10 mhz, v cc = 3.3 v, v i = 0 v or v cc 25 pf
mc74lcx125 http://onsemi.com 5 waveform 1 propagation delays t r = t f = 2.5 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v cc 0 v v oh v ol dn on t phl t plh waveform 2 output enable and disable times t r = t f = 2.5 ns, 10% to 90%; f = 1 mhz; t w = 500 ns v cc 0 v 0 v oe n on t pzh 3.0 v t phz t pzl t plz on vmi vmi vmo vmo figure 3. ac waveforms v cc v oh 0.3 v v ol + 0.3 v gnd symbol v cc 3.3 v 0.3 v 2.7 v 2.5 v 0.2 v vmi 1.5 v 1.5 v v cc /2 vmo 1.5 v 1.5 v v cc /2 vmi vmi vmo vmo
mc74lcx125 http://onsemi.com 6 pulse generator r t dut v cc r l c l c l = 50 pf at v cc = 3.3 0.3 v or equivalent (includes jig and probe capacitance) c l = 30 pf at v cc = 2.5 0.2 v or equivalent (includes jig and probe capacitance) r l = r 1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) figure 4. test circuit
mc74lcx125 http://onsemi.com 7 package dimensions so14 case 751a03 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 so14 case 96501 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m a b c d e e 0.50 m z
mc74lcx125 http://onsemi.com 8 package dimensions tssop case 948g01 issue o dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l u seating plane 0.10 (0.004) t ??? ??? section nn detail e j j1 k k1 detail e f m w 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t v 14x ref k n n on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74lcx125/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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